\section{Experiments and Results}\label{sec:result}

In this section, we evaluate ISL, with the example of superimposed mesh
networks (Section~\ref{sec:interconnet}), by comparison against its 2D counterpart
 and a 3D design without ISL, in chip area, cost, and performance.

\subsection{Area estimation}

In 3D stacking, multiple layers may or may not have the same die
area. As we mentioned in Section~\ref{sec:cost-model}, the total
cost of 3D stacking is related to the area of each layer and we
distinguish the cost for different layers. For our ISL design, we
can distribute the routers aligned with the cores (one router is
vertically below one core).  Or, we can minimize the area of this
layer by centralizing/shrinking the routers with redistribution
interconnect layer in both core layer and cache layer, if the two
mesh networks consume less real estate than other two layers. In the
latter,
 one extra metal may be added to the core and cache layers for
the horizontal routing. The area of ISL includes router area and
link area for two mesh topologies, the interface area and link area
to connect two networks, and TSV area occupied for signal and power
delivery.

We estimate the router area $A_{router}$ by using McPAT~\cite{mcpat}
based on 45nm technology. In order to support layer-to-layer
communication in 3D stacking, hybridization of 2D NoC routers with
Through Silicon Buses (TSB, which consists of many TSVs) requires
one additional link on each NoC router, because TSB can move data
both
upward and downward~\cite{3d:isca06}. %The parameters of the router
%is listed in Table~\ref{tab:router}.
We feed related parameters into
McPAT and obtain the router area 0.93$mm^{2}$. %(if change the virtual
%channel per port to 4, the router area is 4.45$mm_{2}$!).
The area of the link depends on the wire width and space as well as
wire length, which can be changed in ISL depending on the area of
routers and the interface design between two mesh
topologies. %(If we design router to be larger, it may provide
%performance improvement as long as there is enough area for it. The
%minimum link area is related to the interface area between two
%networks). The repeaters and latches is also considered in the total area.
%(normally the width of 128 wires is smaller than the router
%length. if wire pitch is 1um, then the total width is 0.128mm, 1024
%wires:1.24mm. In this case, the link width will not exceed the one
%side of the router).

%\begin{wraptable}{r}{0.6\textwidth}
%\begin{table}[htb]
%\scriptsize %\vspace{-0.5cm}
%\begin{center}
%\caption{\protect\small Router parameters.} \label{tab:router}
%%\setlength{\tabcolsep}{0.2mm}
%\begin{tabular}{||c|c||} \hline
%\hline  Input ports & 6 \\
%
%\hline  Output ports & 6 \\
%
%\hline  Virtual channel per port & 2\\
%
%\hline  Flit bits & 128 \\
%
%\hline  Input buffer entries per Virtual channel & 16 \\
%
%\hline  Number of crossbars & 1 \\
%
%\hline\hline
%
%\end{tabular}
%
%\end{center}
%\end{table}
%\end{wraptable}

In our ISL example, there are 45 signal TSBs (6x6 + 3x3 = 45) pierce
through all three layers.  We provide one TSB for each core in the
structure. Consider the range of TSV pitch size of $1-100\mu m$,
%~\cite{3d:ibm},
the area of one TSB $A_{TSB}$ for a 1024-bit TSB (one cache line)
would consume different area overhead depending on the TSV pitch.
Note that we assume face-to-back bonding in our 3D design so that
TSVs are formed by punching through the silicon substrate, resulting
in extra area. Table~\ref{tab:tsv-size} summarizes the area for a
single TSB (1024 TSVs) depending on different TSV pitch. If the TSV
pitch is smaller than $10\mu m$, the TSB area overhead may be
negligible. %but if the TSV pitch is larger than $10\mu m$, it needs
%to be considered in the total area.
However, when the TSV pitch is larger than $60\mu m$, the area of
one TSB is even comparable to the area of one core. We assume the
maximum TSV pitch in our cost evaluation is $40\mu m$. The
estimation of TSVs for the power delivery is based on the model
proposed in Section~\ref{sec:cost-model}. Assume $P$ is $100W$,
supply voltage is $1Volt$, the resistance of one single TSV is
$40m\Omega$~\cite{tsv-isqed07}, and the voltage drop is 1\%, then
the number of TSVs needed is 400. Considering larger TSV resistance
and higher power consumption, the number of TSVs for power delivery
is increased but we expect it will not exceed 2 TSBs used for
signals (2048). To summarize, we consider the area overhead caused
by TSVs to be 47 TSBs.

\begin{table}[htb]
\scriptsize \vspace{-0.5cm}
\begin{center}
\caption{The area of one TSB (1024 TSVs).} \label{tab:tsv-size}
%\setlength{\tabcolsep}{0.2mm}
\begin{tabular}{|c|c|c|c|c|c|c|c|c|} \hline
%\hline  TSV pitch($\mu m$) & 1 &  10 & 20 & 40 & 60 & 80 & 100\\

%\hline  TSB area($mm^{2}$)&  0.001  & 0.103 & 0.411 & 1.645 & 3.699 & 6.58 & 10.28 \\

\hline  TSV pitch($\mu m$) & 1 &  10 & 20 & 40 & 60 &  100\\

\hline  TSB area($mm^{2}$)&  0.001  & 0.103 & 0.411 & 1.645 & 3.699 & 10.28 \\

\hline\hline
\end{tabular}
\end{center}
\vspace{-0.5cm}
\end{table}



We use a bus to connect the two meshes, due to its high bandwidth and low latency for
local communications~\cite{noc:hpca09}. If we assume the link/bus
can be routed over the routers then the minimum area for the ISL is
only the area of routers plus some routing overhead. Nonetheless, a range of ISL
area is evaluated in the cost analysis.

%The minimum area of interconnect layer %The minimum distance space
%between two fine grained routers is the length of one coarse grained
%router ($1mm$) if we assume the link can be routed over the routers.
%The minimum area of interconnect layer is $(1*5+6)^2=121mm^2$ (the
%area estimation may still be too large, the minimum area is only
%router area plus 30\% overhead? but in the cost analysis, it
%varies).


%The total interconnect layer area is calculated as:
%
%$A_{total}=A_{router}\cdot N_{router} + A_{TSB}\cdot N_{TSB} +
%A_{Link} + A_{Interface}$
%
%where $N_{router}$ and $N_{TSB}$ are the number of routers and TSBs,
%respectively, $A_{Link}$ is the area of the link, $A_{Interface}$ is
%the area of the interface connecting two networks.

\subsection{Cost analysis}

\subsubsection{Die cost without volume analysis}

In this section, we analyze the die cost (without volume
consideration) for ISL design with different area consumption and
compare it against its 2D counterpart and a 3D design without ISL. In our ISL
example design, the area of the core and cache layer is 228$mm^{2}$
without TSV area overhead. If the TSV area overhead is considered
then the maximum extra area caused by TSVs is 75$mm^{2}$ ($40\mu m$
pitch), which is $1/4$ of the total die area of processor die. The
area of ISL may be changed depending on the router design, the
interface design between two mesh networks, and the TSV area
overhead. In order to perform comprehensive analysis, the ISL area
is varied from 60$mm^{2}$ to 228$mm^{2}$ without TSV overhead. We
also evaluate TSV area overhead with different TSV pitches. Three
TSV area overhead cases are evaluated: 0$mm^{2}$, 30$mm^{2}$, and
75$mm^{2}$. The default number of metal layers is 9, 6, and 6 for
core layer, cache layer, and ISL, respectively. When ISL area is
smaller than core and cache layers, one extra metal layer is needed
in core and cache layers
for horizontal routing to connect to TSBs. %Table~\ref{tab:cost}
%provides the cost of core layer, cache layers, ISL layer with
%different areas, and the total cost for different ISL areas
%including 3D bonding cost (2.09 in this case).
Fig.~\ref{fig:tsv-overhead} illustrates the cost comparison for
different ISL area and TSV area overhead. The X-axis represents the
ISL area for different routers and interface design. We observe that
the total cost increases with the increased ISL area. When the ISL
area is smaller than the core and cache layers one extra metal is
needed for core and cache layer for the routing; however, the cost
reduction caused by reduced ISL area offsets the extra metal cost.
We also observe that the extra cost caused by TSV area overhead
could be significant if TSV pitch is large. This indicates that it
is important to take the TSV area into account when we evaluate 3D
at early design stage.

\begin{figure}[htbp]
%\vspace{-8pt}
\centering
\includegraphics[width=3in]{./figure/tsv-overhead.eps}
\vspace{-6pt} \caption{Cost comparison for different ISL area and
TSV area overhead.} \label{fig:tsv-overhead} %\vspace{-8pt}
\end{figure}

%\begin{table}[htb]
%\scriptsize %\vspace{-0.5cm}
%\begin{center}
%\caption{\protect\small The total cost depending on different ISL
%area without TSVs area overhead(normalized unit).} \label{tab:cost}
%%\setlength{\tabcolsep}{0.2mm}
%\begin{tabular}{||c|c|c|c|c|c||} \hline
%\hline  Area of ISL ($mm^{2}$) & 144 & 164 & 184 & 208 & 228  \\
%\hline  core layer cost& 65.49 (10) & 65.49 (10)& 65.49 (10)& 65.49 (10)& 63.40 (9)\\
%\hline  cache layer cost & 59.22(7)  & 59.22(7) & 59.22(7)& 59.22(7) & 57.13 (6)\\
%\hline  ISL cost & 30.20 (7) & 35.59(7) & 41.40 (7)& 47.93(7) & 57.13 (6)\\
%%\hline  Total cost & 154.91  & 160.3 & 166.11 & 172.64 & 177.66\\
%\hline  Total cost & 157.0  & 162.39 & 168.20 & 174.73 & 179.75\\

%
%\hline\hline
%\end{tabular}
%\end{center}
%\end{table}

%JL: Where is 3D bonding cost, wafer thinning cost, etc taken care of?

We also evaluate the cost for 2D design and 3D design without ISL.
For 2D design, we place 36 cores, 36 L2 cache banks, and
fine-grained mesh network in one layer. Without loosing generality,
the area of the mesh network also varies depending on the router
design and the link area. The 36 cores and 36 cache banks consume
460$mm^{2}$. We assume the total area ranges from 510 to 600$mm^{2}$
(510, 540, 570, 600 with 9 metals), the total cost is 258.49,
289.80, 322.53, and 359.61 for these four cases, respectively. We
see that even with smallest network area, the cost of 2D design is
much higher than that of 3D with ISL (maximum area) or comparable to
3D with ISL with maximum TSV area overhead. The cost reduction of 3D
with ISL (maximum area) is about 40\% compared to 2D even with the
smallest interconnect area if no TSV area overhead is considered.
However, if maximum TSV area overhead is considered in 3D, the cost
is about 6\% higher than 2D with smallest network area.

For 3D design without ISL, the routers are integrated with cache
layer (or computing layer) so that there are two layers in total.
Similarly, the area of these two layers is changed from 280 to
400$mm^2$ (6 cases: 280, 300, 320, 340, 360 and 400) depending on
the router design and TSV area overhead. The total cost is 164.84,
184.58, 206.57, 229.8, 258.47, 286.09, 313.61 for these 6 cases. We
find that 3D with ISL is most cost efficient if TSV area overhead is
reasonable but the exact boundary for TSV pitch depends on the
design itself. Therefore, it is essential to take the TSV area,
including signal and power delivery etc, into account, when we
evaluate a 3D design at its early stage.


\subsubsection{Volume analysis}

\begin{figure}[htbp]
%\vspace{-8pt}
\centering
\includegraphics[width=3in]{./figure/volume.eps}
\vspace{-8pt} \caption{Volume analysis for non-reuse and reuse.}
\label{fig:volume} %\vspace{-10pt}
\end{figure}

In our ISL architecture design, the ISL could be stacked with
different functional units (e.g., different number of cores) and
various capacity of storage (different capacity of L2 Cache). With
die reuse, the total cost for multiple applications could be
reduced. Assume we have two 3D designs, each with 3 layers. The
first design has 36 cores as layer 1, interconnect layer as layer 2,
36M L2 Cache as layer 3. The second design has 9 cores as layer 1,
interconnect layer as layer 2, 9M L2 Cache as layer 3. If no reuse
is enabled, the total cost for these two designs is calculated as
$$Cost_{total}=\sum^6_{i=1} (NRE_{i}/Volume_{i}) + \sum^2_{j=1}
3D_{j}$$ There are total 6 layers in these two designs and each
layer has its own NRE cost and volume. With the reuse, since the NRE
part of the total cost is reduced, i.e., two ISL layers use the same
design, thus only one design cost and mask cost need to be
considered. Here we provide an example to illustrate the volume
impact on the total cost for these two applications.

We obtain $3D_{j}$ from our cost model without volume consideration.
For volume related cost at 45nm technology, the design cost and mask
cost are either from or scaled from~\cite{nre-cost}. Note that we
assume 3D design does not introduce extra design cost compared to 2D
once the 3D design flow
is mature. %The design cost for design 1 is $40million/die$. The
%design cost for design 2 is $40million$ for ISL and $10million$ for
%core and cache layers due to their smaller area. The mask cost is
%$9million$ for each die. We assume these two designs have the same
%number of volume $N$ which may range from $1m$ to $50m$. The cost
%for the non-reuse case is calculated by
%$(40+40+40+10+40+10+9*6)million/N+3D_{1}+ 3D_{2}$, in which $3D_{1}$
%and $3D_{2}$ are 180 and 130, respectively. %$234m/N+3D_{1}+ 3D_{2}$)
%The cost for reuse case is
%$(40+40+10+10+9*4)million/N+(40+9)million/2N+3D_{1}+ 3D_{2}$. (may
%hide the exact design cost and mask cost).
%($160.5m/N+3D_{1}+ 3D_{2}$).
Fig.~\ref{fig:volume} illustrates the cost comparison between the
non-reuse and reuse cases. The result shows that the reuse is very
cost effective when the volume is low.  However, when the volume is
very high, the NRE cost is not dominant then the cost difference is
reduced. Note that if the cache layer can also be reused (have the
same capacity for these two applications) then the cost reduction
will be improved.
%In summary, we provide a volume analysis example and
%demonstrate the potential cost reduction by reusing our ISL design.


%\begin{table}[htb]
%\scriptsize %\vspace{-0.5cm}
%\begin{center}
%\caption{\protect\small The total cost considering different
%volume.} \label{tab:volume}
%%\setlength{\tabcolsep}{0.2mm}
%\begin{tabular}{||c|c|c|c|c|c|c||} \hline
%\hline  Volume & 1m & 2m & 5m & 10m & 20m &50m\\
%\hline  no reuse&  & & & & &\\
%\hline  reuse &   &  &  & & &\\
%
%\hline\hline
%\end{tabular}
%\end{center}
%\end{table}


%\begin{itemize}
%\item 3D 3 layers with decoupling: 1) Every layer is 230mm2 with default metal
%layers, Processor (9etal): 63.40, Cache (6etal): 57.13,
%Interconnect (230mm2) (6etal): 57.13, the total cost is 177.66; 2)
%2 layers are 230mm2 (core and cache layer), interconnect layer is
%144, 164, 184, 204 (different area cases), the core and cache layer
%use one more metal layer, Processor (10etal): 65.49, Cache
%(7etal): 59.22, Interconnect (6etal): 30.20, 35.59, 41.40,
%47.93, the total cost is 154.91, 160.3, 166.11, 172.64
%
%\item 3D 2 layers without decoupling: cache layer and processor layer, the router is in
%the cache layer, 2 layers with the same area 280, 300, 320, 340mm2.
%Processor (9etal): 86.88, 97.34, 109.00, 121.32. Cache+Router
%(280mm2) (6etal): 77.96, 87.24, 97.57, 108.48. The total cost is
%164.84, 184.58, 206.57, 229.8
%
%\item 2D case: the area is 510, 540, 570, 600mm2 (9etal): 258.49, 289.80, 322.53, 359.61
%\end{itemize}

%Xiangyu's experiments:
%
%1) 3 layers with 228mm2 each, or 2 layers 228mm2 with extra metal
%and 1 layer area based on Table~\ref{tab:cost}.
%
%2) 2D cost: at least larger than 228+228+75=531, the number of
%routers?
%
%3) 2 layers with 228+75=303 each
%
%4) volume analysis

%1. area estimation of the interconnect layer: 1) the area of
%interconnect layer is the same as compute layer and cache layer; 2)
%if the area of this layer is smaller, how to connect the layer with
%compute/cache layers, may need extra metal layer if don't want to
%increase the area of compute/cache layers.
%
%2. performance and power results with different latency of the
%communication, different cache size, different number of cores.
%
%3. cost analysis for different number of cores in the cache layer
%with different cache capacity. cost analysis for different
%manufacture volume. alignment issue when the number of cores is
%different. (if can get package cost would be better)
%
%4. comparison cases? compared to 2D and 3D with coupled interconnect
%layer (interconnect layer is integrated with compute/cache layer)

\subsection{Performance result}

\begin{figure}[htbp]
\vspace{-8pt} \centering
\includegraphics[width=2.5in]{./figure/2d-3d-config.eps}
\vspace{-8pt} \caption{System configurations for 2D, 3DB, and 3DI
cases.} \label{fig:2d-3d-config} \vspace{-10pt}
\end{figure}

%In this section, we evaluate the performance result for our proposed
%design and compare it with 2D and 3D baseline (only fine-grained
%network).
We first examine the performance of the example ISL
architecture with 36 cores. The cache size is estimated based on the
area of cache layer using Cacti~\cite{3D:CACTI}. For 36-core system,
we assume there is a 36-bank shared L2 cache with 36MB capacity.
Each core is connected to a cache bank using TSB. The cache
controller is
integrated with the processor layer. %(cache can have 2 layers for
%larger capacity, about 0.15M/mm2)
The floorplans for these three cases are shown in
Fig.~\ref{fig:2d-3d-config} (only 4 cores are illustrated for the
simplicity). Fig.~\ref{fig:2d-3d-config}(a) illustrates 2D
configuration, in which one core and one cache bank is placed
together and connected to other cache/bank groups by routers.
Fig.~\ref{fig:2d-3d-config}(b) shows 3D baseline (3DB), in which the
fine-grained mesh network is integrated with core layer.
Fig.~\ref{fig:2d-3d-config}(c) shows 3D design with ISL (3DI), in
which both coarse-grained and fine-grained mesh networks are
integrated in ISL. In 3DI, the coarse-grained mesh reduces the
number of hops for global communication. In 2D case and 3DB cases,
there is only fine-grained mesh network to support the
communication. In 2D case, the link latency is larger due to longer
link between two routers. Fig.~\ref{fig:performance-36} illustrates
the IPC comparison of these three cases, normalized to 2D case.
While it varies between applications, the result shows that 3DI
achieves 21\% and 6.5\% average performance improvement over 2D and
3DB, respectively.


\begin{figure}[htbp]
\vspace{-8pt} \centering
\includegraphics[width=3in]{./figure/performance-36.eps}
\vspace{-8pt} \caption{Performance comparison among 2D, 3DB, and 3DI
cases.} \label{fig:performance-36} \vspace{-10pt}
\end{figure}

\begin{figure}[htbp]
\vspace{-8pt} \centering
\includegraphics[width=3in]{./figure/performance-9.eps}
\vspace{-8pt} \caption{Performance comparison between multiple
networks and coarse-grained network.} \label{fig:performance-9}
%\vspace{-10pt}
\end{figure}

We also evaluate the performance of the example ISL architecture
with 9 cores, and compare the proposed superimposed (coarse+fine grained) networks with coarse-grained
mesh network. For 9-core system, we assume there is a 36-bank shared
L2 cache with 9MB capacity. The performance comparison is shown in
Fig.~\ref{fig:performance-9}. The result shows that ISL with superimposed (coarse+fine grained)
networks has 5.5\% performance improvement than the coarse-grained
network. In summary, we show that our ISL design improves
performance by effectively using these two mesh topologies for
different system configurations.


%%%%%%%%%%%%%%%%%
%% JL: Removed due to the page limit of DAC
%%%%%%%%%%%%%%%%%

Finally, we have shown the proposed ISL design improve performance
by supporting the selection of networks for efficient data
communication, e.g., reducing hop counts.  As a result, the
interconnect power consumption is reduced accordingly. In addition,
the thermal is expected not a big concern with reduced power
consumption. Due to limited space, we skip the power and thermal
evaluation results in this paper.

%\subsection{Power result}
%
%%The power of the core is obtained from McPAT~\cite{mcpat}.
%We estimate the power consumption of cache and interconnect by
%collecting the read/write accesses of cache and the number of hops
%from Simics. %For the power consumption of caches, we count the
%%``hit'' and ``miss'' numbers for read and write operations, then we
%%can calculate the total read and write numbers. In addition, we
%%calculate the total number of hops.
%We assume fixed energy consumption for each read access, write
%access and each hop between routers. The read/write energy is from
%Cacti and the router energy is from McPAT. Then the total energy can
%be obtained using the energy number and the statistics from Simics.
%The power is calculated by energy/execution time, in which the
%execution time is the total time to run 3 billion cycles.
%Figure~\ref{fig:power-36} plots the power consumption comparison
%(core power is not included) for 2D, 3DB, and 3DI cases in 36-core
%configuration. The result shows that 3DI consumes even less power
%than 2D and 3DB due to reduced hops. Figure~\ref{fig:power-9}
%illustrates the power comparison for coarse only network and coarse
%plus fine networks in 9-core configuration. Similarly, the latter
%one consumes less power due to reduced interconnect hops. (only
%dynamic power is compared, leakage power is not included)
%
%\begin{figure}[htbp]
%%\vspace{-8pt}
%\centering
%\includegraphics[width=3.5in]{./figure/power-36.eps}
%%\vspace{-10pt}
%\caption{Power comparison among 2D, 3DI, and 3DN cases.}
%\label{fig:power-36}
%%\vspace{-12pt}
%\end{figure}
%
%\begin{figure}[htbp]
%%\vspace{-8pt}
%\centering
%\includegraphics[width=3.5in]{./figure/power-9.eps}
%%\vspace{-10pt}
%\caption{Power comparison between multiple networks and
%coarse-grained network.} \label{fig:power-9}
%%\vspace{-12pt}
%\end{figure}

%Guangyu's experiments:
%
%1) 36 cores, vary communication latency (cycles/hop)depending on
%2D/3D/different router configuration, examine the performance/power
%
%2) 36 cores, different cache size per core, e.g. 1M and 2M,
%performance/power
%
%3) 9 cores
%
%power/cost, volume analysis, other simulations such as
%reconfigurability, recovery if some core is not functional...

%\subsection{Scalability}
%
%If there are more cores, similar topology in the interconnect layer.
%Here is only one example on hierarchical topology.

%also add turn on/off on network evaluation?

%cost result: different technology, layer, different interconnect
%area... performance result, performance/cost result
%
%Table~\ref{tab:cost} gives the preliminary cost results for
%different layers and area cases. In the table, 1 means 1 layer with
%640$mm^{2}$ footprint (2D), 2 means 2 layers with 320$mm^{2}$
%footprint, 2+1/4 means the third layer (interconnect layer) has 1/4
%of the other two layers..., 3 means 3 layers with 213$mm^{2}$
%footprint, 3+1/4 means the fourth layer has 1/4 of the other three
%layers...
%
%some observations:
%
%1) with the technology scales, the cost increases under the same
%chip area.
%
%2) 3D cases have lower cost than 2D with current area constraint.
%
%3) when the interconnect layer is very small, e.g. 1/16 area, it's
%better to integrate it with existing layer instead of a new layer
%(not shown in the table)
%
%one concern: defected chips are considered to be discarded in the
%cost model. however, in CMP, if some cores are not working it can
%still be used even without reconfigurability? only consider
%defect-density related yield.
%
%\begin{table}[!htb]
%%\begin{table}[htb]
%\scriptsize \vspace{-0.5cm}
%\begin{center}
%\caption{\protect\small Cost result for different layers and area.}
%\label{tab:cost}
%%\setlength{\tabcolsep}{0.2mm}
%\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|} \hline
%\hline  Technology & 1 & 2 & 2+1/4 & 2+1/2 & 2+3/4 & 3 & 3+1/4 & 3+1/2 & 3+3/4 & 4 \\
%
%\hline  130nm  & 200.5 & 108.8 & 120 & 129.8 & 145 & 166 & 96 & 101.4 & 108.7 & 118.5\\
%
%\hline  90nm  & 276.6 & 165.6 & 184.8 & 200.6 & 222.4 & 251.2 & 157.3 & 166.3 & 177.6 & 191.5\\
%\hline  65nm   & 285.2 & 170 & 189.4 & 205.8 & 228.3 & 258 & 160.9 & 170 & 181.5 & 196\\
%\hline  45nm   & 308.1 & 180.9 & 200.7 & 218 & 242.2 & 274.2 & 168 & 177.7 & 190.1 & 205.7\\
%
%\hline\hline
%
%\end{tabular}
%\vspace{-0.5cm}
%\end{center}
%\end{table}
